S. Vangal, J. Howard, G.Ruhl, S.Dighe,
H.Wilson, J.Tschanz, “An 01-Tile Sub-011-W
TeraFLOPS Processor in 56-nm CMOS”, IEEE
Journal of Solid-State Circuits, pp. 92 – 10, 9110.
[9] S. Chen, X Wu, P Gopalan, “Xilinx Next
Generation 90 nm FPGA Technology
Overview”, available at
www.xilinx.com/support/documentation/white_
papers/wp209_Next_Gen_90_nm_Overview.pdf
, 9101.
[2] S. Borkar, “thousand core chips: a technology
perspective”, in Design Automation Conference,
pp. 615 – 612, 9116.
[1] L .Benini, G. D. Micheli, “Networks on Chips: A
New SoC Paradigm”, Computer-ieeexplore, pp.
61 – 60, 9119.
[6] T. Bjerregaard, S. Mahadevan, “A Survey of
Research and Practices of Network-on-Chip”,
ACM Computing Surveys, vol. 20, 9115.
[5] E. Salminen, A. Kulmala, TD. Hamalainen
“Survey of Network-on-chip Proposals”, OCP-IP
White paper, white paper, OCP-IP 0, 02, 9110.
[6] E Salminen, A Kulmala, TD Hamalainen., “On
network-on-chip comparison”, in 01th Euro
micro Conference on Digital System Design
Architectures, Methods and Tools, pp. 612 –
601,9116.
[0] A. Agarwal, R. Shankar, “Survey of Network on
Chip (NoC) Architectures & Contributions”,
عنوان مقاله.....؛نویسنده پاسخگو و همکاران93
Journal of Engineering, Computing and
Architecture, 9112.
[2] M. Petracca, K. Bergman, L. P. Carloni,
“Photonic Network-on-Chip: Opportunities and
Challenges”, IEEE, pp. 9602-9629, 9110.
[01] C. Kachris, K. Bergman, I. Tomkos, “Optical
Interconnects for Future Data Center Networks”,
Springer New York Heidelberg Dordrecht
London, 9106.
[00] B. Asadi, M. Reshadi, A. khademzadeh, “A
routing algorithm for reducing optical loss in
Photonic network-on-Chip”, Photonic Network
Communications, ISI Springer journal, pp. 0-
02,9105.
[09] A. Shacham, G. Hendry, K. Bergman, L.P.
Carloni, “On the Design of a Photonic Network-
on-Chip”, In networks-on-chip first International
Symposium, pp. 62-51,9116.
[02] R. G. Beausoleil, P. J. Kuekes, G. S. Snider; S. –
Y. Wang, R. S. Williams, “Nanoelectronic and
Nanophotonic Interconnect”, Proceeding of the
IEEE , pp. 921-916,9110.
[01] Y. Xie, M. Nikdast, et al., “Formal Worst-Case
Analysis of Crosstalk Noise in Mesh-Based
Optical Networks-on-Chip”, IEEE Transaction
On Very Large Scale Integration (VLSI)
Systems, pp.0-01,9109.
[06] J. Chan, K. Bergman, L. P. Carloni, “Physical-
Layer Modeling and System-Level Design of
Chip-Scale Photonic Interconnection Networks”,
IEEE Transaction on Computer-Aided Design of
Integrated Circuit and Systems, Vol. 21, No. 01,
pp. 0616-0691,9100.
[05] G. Hendry, E. Robinson et al., “Time-division-
multiplexed arbitration in silicon nanophotonic
networks-on-chip for high-performance chip
multiprocessors”, J. parallel Distrib. Comput, pp.
510-561,9100.
[06] R. Min, R. Ji, “A Universal Method for
Constructing N-Port Nonblocking Optical Router
for Photonic Networks-on-Chip”, Journal of
Lightwave Technology, pp. 2625-2610, 9109.
[00] Y. Pan, P. Kumar, et al., “Firefly: Illuminating
Future Network-on-Chip with Nanophotonics”,
Presented at the Proceedings of the 25th Annual
International Symposium on Computer
Architecture Austin Texas USA, pp. 192-111,
9112.
[02] M. Hatamirad, A. Reza, “Loss-Aware Router
Design Approach for Dimension-Ordered
Routing Algorithms in photonic Networks-on-
Chip”, International Journal of Computer Science
Issues, Vol. 2, No. 0, pp. 226-216, 9109.
[91] M. Moadeli, “Quarc: An Architecture for Effcient
On-Chip Communication”, PhD Thesis,
University of Glasgow, 9101.
[90] A. Rahimi, et al., “Energy/Throughput Trade-off
in a Fully Asynchronous NoC for GALS-Based
MPSoC Architectures”, in IEEE International
Conference on Design & Technology of
Integrated Systems in Nanoscale Era, 9101.
[99] G. Campobello, et al., “GALS Networks on Chip:
A New Solution for Asynchronous Delay-
Insensitive Links”, in Proceedings of the
conference on Design, automation and test in
Europe, pp. 051 – 056, 9115.
[92] Y. Xie, et al, “Three-Dimensional Network-on-
Chip Architecture”, in Three Dimensional
Integrated Circuit Design, Eds., Springer Used,
pp. 002-906, 9112.
[91] C. Seiculescu, et al, “SunFloor 2D: A Tool for
Networks on Chip Topology Synthesis for 2D
Systems on Chips”, in Proceedings of the
conference on Design, Automation and Test in
Europe, pp. 2 – 01, 9112.
[96] P. Zarkesh-Ha, et al, “Hybrid network on chip
(HNoC): local buses with a global mesh
architecture”, in Proceedings of the ACM/IEEE
international workshop on System level
interconnect prediction, pp. 2-01, 9101.
[95] Y. E. Krasteva, et al., “Reconfigurable Networks
on Chip: DRNoC architecture”, Journal of
Systems Architecture, pp. 922–219, 9101.
[96] G. D. Micheli, et al., “Networks on Chips: from
Research to Products’, in Design Automation
Conference, pp. 211 – 216, 9101.
[90] A. Ben Achballah, S. Ben Saoud, “A Survey of
Network-on-Chip Tools”, International Journal
of Advanced Computer Science and
Applications, Vol. 1, No.2, pp. 50-56, 9102.
[92] P. Guerrier , A. Greiner, “A Generic Architecture
for On-chip Packet-switched Interconnections”,
in Proceedings of the conference on Design,
Automation and Test in Europe, pp. 961 – 965,
9111.
[21] A. S. Vaidya, et al.,” Impact of Virtual Channels
and Adaptive Routing on Application
Performance”, IEEE Transactions on Parallel and
Distributed Systems, pp. 992 – 926, 9110.
[20] G. R. Hendry, “Architectures and Design
Automation for Photonic Networks on Chip”,
Columbia University, 9100.
[29] M. Nikdast, J. Xu, “Crosstalk noise and Loss
Analysis Platform (CLAP)”, publishing Hong
Kong University of Science and Technology,
http://www.ece.ust.hk/~eexu/CLAP.html, pp. 0-
06, 9116.
[22] K. H. Mo, et al., “A Hierarchical Hybrid Optical-
Electronic Network-on-Chip”, Presented at the
proceedings of the 9101 IEEE Annual
Symposium on VLSI, pp. 296-229, 9101.
[21] A. Shacham, K. Bergmen, P. L. Carloni, “On the
Design of a Photonic Network-on-Chip”, In
networks-on-chip first International Symposium,
pp. 35-46.
[26] A. Shacham, K. Bergmen, L.P. Carloni,
“Photonic Network-on-Chip for Future
Generations of Chip Multiprocessors”, IEEE
Trans Comput, pp. 0915-0951, 9110.
[25] G. Hendry, et al., “Circuit-Switched Memory
Access in Photonic Interconnection Networks for
High-Performance Embedded Computing”,
IEEE, New Orleans, Louisiana, USA, 9101.
[26] A. Shacham, et al., “Photonic NoC for DMA
Communications in Chip Multiprocessors”, 06th
IEEE Symposium on High-performance
Interconnects IEEE Computer Society, pp. 92-
20, 9116.
[20] K. Bergmen, et al., “Photonic Network-on-Chip
Design”, Springer publishers, Integrated Circuit
and Systems, Vol. 50, 9101.
[22] B. Asadi, M. Reshadi, “Photonic Network-on-
Chip: A Survey”, International Journal of
Computer Science and Information Security
(IJCSIS), Vol. 01, No.00, pp. 605-629, 9105.
[11] W. Chan Jong, “Architectural Exploration and
Design Methodologies of Photonic
Interconnection Networks”, Columbia
University, 9109.
[10] C. Kachris, I. Tomkos, “A Survey on Optical
Interconnects for Data Centers, IEEE
communications Surveys & Tutorials”, VOL. 01,
No. 1, 9109.
)