Dead time refers to a period of time in which the single photon detector is not able to detect a new photon due to the effects caused by the detection of the incoming photon and during the reset process. Due to the importance of the role of dead time in limiting the detection frequency of single-photon avalanche detectors and limiting the exchange rate in various systems such as quantum key distribution, measuring this characteristic in single-photon detectors is important. In the proposed method of this research, an FPGA chip is used to measure the dead time in single photon detectors. The proposed FPGA model is XC7A35T from the Artix family owned by Xilinx. A circuit is designed for the detector test using VHDL hardware design code and it provides the possibility of determining the dead time on the SPAD by controlling the single photon production source and the detector simultaneously.
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